RE: [sv-bc] Does named modport port represent any data type?

Surya,

 

I want to add that the following references to P and Q in your example:

 

initial i.P = i.Q;

 

are not hierarchical references, they are interface port references.

 

The reason for the distinction is that a module, M, needs to have access
to the types and parameters defined in the interface it is connected to
since the module is not defining its own port signals. If you treat them
as hierarchical references, you would not be able to define derivative
types and variables that normally occur inside a module.

 

Dave

 

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Brad Pierce
Sent: Friday, September 15, 2006 8:44 AM
To: sv-bc@server.eda-stds.org
Subject: Re: [sv-bc] Does named modport port represent any data type?

 

Surya,

 

According to 20.4.4, 

 

       "The self-determined type of the port expression becomes the type
for the port."

 

Modport expressions are not defined in terms of the 1995 construct.

 

-- Brad

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Surya Pratik Saha
Sent: Friday, September 15, 2006 12:26 AM
To: sv-bc@eda-stds.org
Subject: [sv-bc] Does named modport port represent any data type?

Hi, 
In SV 1800 LRM, following e.g. is given (section no. 20.4.4 Modport
expressions, page no. 359): 
interface I; 
logic [7:0] r; 
const int x=1; 
bit R; 
modport A (output .P(r[3:0]), input .Q(x), R); 
modport B (output .P(r[7:4]), input .Q(2), R); 
endinterface 
module M ( interface i);, 
initial i.P = i.Q; 
endmodule 
module top; 
I i1; 
M u1 (i1.A); 
M u2 (i1.B); 
initial #1 $display("%b", i1.r); // displays 00010010 
endmodule 

Here hierarchical reference is applied on named modport port 'P' and
'Q'. But do they represent any data type? 

LRM is not clear on that. If we consider equivalent e.g. with named port
in module port declaration corresponding to Verilog 2005 LRM: 
module top (.A(x), .B(y)); 
        input x,y; 
endmodule 

module test; 
        assign top.A = 1; 
endmodule 

This is invalid case. As  'A' does not represent any data type. So I
think the e.g. provided in SV LRM is wrong. 

-- 
Regards
Surya.