Re: [sv-bc] Is "var" required for real ports?

>From: "Stuart Sutherland" <stuart@sutherland-hdl.com>

>I has been brought to my attention that one SV simulator requires a "real"
>module port to be declared as "var real", and other simulator as just
>"real".  I cannot find any justification in the LRM for "var" being required
>to declare a real port.  This difference in simulators is third-hand...I
>don't have the product licenses to test the claim.
>
>If "var" is required, can anyone point me to exactly where that is specified
>in the LRM?

This would only apply to module input ports.  It is not a syntactic
requirement; it is a semantic one created by the fact that the LRM does
not yet allow reals on nets.

Section 19.8 states for module ports

"For input and inout ports, if the port kind is omitted, then the port
shall default to a net of net type wire.  This default net type can be
changed using the `default_nettype compiler directive, as in Verilog."

Section 6.5 specifies a restricted set of data types that are allowed
for nets, which does not include reals.

So a declaration of a module input port of type real would be a declaration
of a real net, which would be an error.  If the port is declared to be a
variable using the var keyword, then it becomes legal.

There are a variety of reasons why a simulator might be allowing the var
keyword to be omitted.  It might not have implemented the 1800 extensions
to allow datatypes on nets, or the port rules in 19.8.  It might choose
to treat the port as a variable when treating it as a net would produce
an error.  I believe one of the versions of the proposal for section 19.8
proposed a rule something like that, which was rejected.

Steven Sharp
sharp@cadence.com