Re: [sv-bc] 19.12.5: array of instances connection to packed array port

>I did not understand the phrase "starting with all right-hand indices to
>match the rightmost part-select". Can someone clarify, maybe with an
>example?

I am guessing, but I think I know what it means.  Consider a packed array

logic [1:0] [2:1] [7:6] ar;

and an equal width vector

logic [7:0] v;

If you connect either one to an array of 2 instances, each with a 4 bit
wide port, then each instance will get a 4-bit part-select of the 8 bit
wide connection.  The instance with the rightmost index in the instance
array will be connected to the rightmost part-select.  With the vector,
that would be v[3:0], because that is the rightmost part-select.  

What this phrase is trying to say is that the rightmost connection for
the packed array is the 4-bit chunk that starts from all the right-hand
indices of the packed array.  In other words, where the vector starts 
with v[0] as the rightmost, the packed array starts with ar[0][1][6] as
the rightmost.  That is the bit with all right-hand indices.

It is somewhat awkward to describe, since you can't actually apply a
4-bit part-select to ar in the Verilog code.  An attempt to take a
part-select will look like an array slice.  What you are trying to do
is grab a 4-bit part-select from the vector equivalent of the array,
ignoring the fact that it has any subdivisions.  The rules for connecting
packed arrays to instance array ports ignores the fact that it was a
packed array, and just treats it like a vector of the same width.

Steven Sharp
sharp@cadence.com