RE: [sv-bc] Re: Package export proposal

 Gordon,

Would you also allow to export symbols inside a design unit other than a
package?
And consequently top.x would be allow to refer to the same as p1::x?

module top;
import p2::*;
export p2::*;
  initial
        x = 9; // This imports and exports symbol x from p2 which is an
alias of p1::x

endmodule

module fake_oomr;
   top.x = 10; // This is an alias of p2::x alias of p1::x
endmodule

I am really against this. This is blurring the line between oomrs and
package references.

I was hoping that the proposal would also provide visibility to exported
symbols and 
not creating a new declaration. If we go with creating a new
declaration, 
we have to define the semantics to assigning to an aliased declaration. 

I would prefer that the export only makes the symbol from p1::x,
directly visible 
if someone imports p2. This provides transitivity of the imports without
changing
the qualifying name for the symbol.

Francoise
    '


-----Original Message-----
From: Gordon Vreugdenhil [mailto:gordonv@model.com] 
Sent: Friday, September 22, 2006 5:28 PM
To: Francoise Martinolle
Cc: Greg Jaxon; Bresticker, Shalom; Brad Pierce; sv-bc@eda-stds.org
Subject: Re: [sv-bc] Re: Package export proposal

Francoise,

I am viewing an "export" as essentially a shorthand to a VHDL alias
declaration.  So in the case of p2, we have the conceptual declaration:
    alias p1::x x;

This means that you *can* refer to just "p2::x" in other places and have
that resolve to the declaration that originates in p1::x.  Due to
package dependency rules, we know that any such reference to p2 would
require p1 to already exist (due p2's dependency on p1) so all of this
is resolvable at compile time.

Gord.

Francoise Martinolle wrote:

> Gordon,
> 
> I read the proposal and I have a question regarding the comments for
> "p2":
> 
> package p1;
> 
>    int x,y;
> 
> endpackage
> 
>  
> 
>  
> 
> package p2;
> 
>    import p1::x;
> 
>    export p1::*;    // exports p1::x as the name "x"; 
> 
>                     // p1::x and p2::x are the same declaration
> 
> endpackage
> 
>  
>  
> 
> The comment I have problems with is: "p1::x and p2::x are the same 
> declaration.
> It seems to infer that you can refer to x in package p1, as either 
> p1::x or p2::x.
> 
> I do not like this. The export should only make the symbol x imported 
> by
> p2 directly visible
> by design units importing p2.
> For example in module top I cannot refer to x as p2::x can I? Only 
> p1::x is a legal full qualified reference for x.
> 
> 
> Francoise
>     '

--
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com