Yes on all except 1119 and 1209, for the reasons stated below. SVDB 0967 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000967 SVDB 0982 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000982 SVDB 1119 ___Yes __X_No http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001119 Reasons -- missing 'end' in example, and incompatible with existing implementations. SVDB 1209 ___Yes _X__No http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001209 Reasons -- missing bolding on keywords, 'struct' instead of 'structure', and wondering why it says both 'aggregate parameter' and 'parameter aggregate'. SVDB 1337 _X__Yes ___No (Close as duplicate of 1334) http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001337 SVDB 1341 __X_Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001341 SVDB 1493 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001493 SVDB 1496 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001496 SVDB 1529 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001529 SVDB 1534 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001534 SVDB 1538 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001538 SVDB 1539 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001539 SVDB 1540 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001540 SVDB 1554 _X__Yes ___No http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001554Received on Wed Sep 27 23:32:27 2006
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