Re: [sv-bc] FW: logic and bit to be changed to the more VHDL-like ulogic and ubit

I assume that this originated from Cliff Cumming's request for feedback
from users on his desire to rename these, back in 2003.  This request
went out in various forms, and was included in his award-winning SNUG
paper of that year.

While I was in favor of some renaming to reduce keyword collisions at
the time, I am afraid it is much too late now.  The IEEE SystemVerilog
standard was approved in 2005 with the existing keywords.

Also, the suggested VHDL-like names are no longer appropriate.  The "u"
in the VHDL names stands for "unresolved".  With the IEEE extensions to
allow some datatypes on nets, logic is now a resolved type when it is used
on a net.  Further extensions may allow nets of bit type that are resolved
also.  Resolution is based on whether an object is a variable or a net
(and the net type of that net) rather than its data type.

On a related note, Verilog-2005 did add a new net type that is always
unresolved.  Based on the same analogy with VHDL unresolved data types,
the net type was called "uwire".

Steven Sharp
sharp@cadence.com