RE: [sv-bc] Email Ballot Due Sep 28

Regarding this and my question (a):

1. The original VXL behavior is irrelevant regarding macro substitution
within strings since VXL behavior changed to be the reverse a long time
ago.

2. I checked various implementations regarding macro substitution and
argument substitution within strings. ALL the implementations, including
those of Synopsys, do NOT do macro substitution within strings, so there
should be no argument about that. That is another reason that the
comment about Verilog-XL is irrelevant, since the quoted reference
referred to macro substitution.

3. Where there IS a difference between implementations is with respect
to ARGUMENT substitution, which is the very reason that `" was created.
There Verilog-XL behavior is not relevant, since it does not support
macros with arguments, according to my experiments. 

However, incompatibility with current implementations is not a valid
argument since different behavior would conflict with other
implementations. Some implementation is going to have to change. The
only way out would be to leave the behavior undefined. In my mind, that
is a worse alternative, as it makes code unportable.

One more argument in favor of defining that argument substitution does
not occur within regular strings is that it allows both non-substitution
and substitution to be implemented, the latter using `".

Regards,
Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Brad Pierce
> Sent: Thursday, September 28, 2006 11:45 PM
> To: sv-bc@server.eda.org
> Subject: Re: [sv-bc] Email Ballot Due Sep 28
> 
> Shalom,
> 
> Maybe `" isn't needed?  The original Verilog-XL didn't need it, as
> described in --
> 
>     http://boydtechinc.com/etf/archive/etf_2003/1543.html
> 
> -- Brad
> 
> -----Original Message-----
> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
> Sent: Thursday, September 28, 2006 3:36 AM
> To: Brad Pierce; sv-bc@eda.org
> Subject: RE: [sv-bc] Email Ballot Due Sep 28
> 
> 1119: You're right about the missing 'end'. I fixed it and uploaded a
> corrected version.
> 
> Regarding incompatibility with existing implementations:
> 
> a. The proposal treats expansion of macro calls and substitution for
> formal argument identifiers the same way, i.e., neither is done within
a
> string. Do the existing implementations you refer to distinguish
between
> them?
> 
> b. If such expansion and substitution are performed within strings,
then
> what is the need for `"?
> 
> c. Since other existing implementations behave as described in the
> proposal, there will be an incompatibility with some existing
> implementations in any case and implementations are incompatible with
> each other. I think the LRM should not leave this ambiguous and needs
to
> choose one of the behaviors.
> 
> 1209: I fixed the problems and uploaded a new version. I changed
> 'parameter aggregate' to 'aggregate parameter' in order to be
consistent
> with the usage in the rest of the LRM.
> 
> Shalom
> 
> 
> > SVDB 1119 ___Yes   __X_No
> > http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001119
> >
> >   Reasons -- missing 'end' in example, and incompatible with
existing
> > implementations.
> >
> > SVDB 1209 ___Yes   _X__No
> > http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001209
> >
> >   Reasons -- missing bolding on keywords, 'struct' instead of
> > 'structure', and wondering why it says both 'aggregate parameter'
and
> > 'parameter aggregate'.