Re: [sv-bc] Mantis 1571: Add default values for macro arguments

> Just noting that despite any other merits, this design is not
> backward compatible with existing uses of macro expansion.

I don't see how new functionality can be added to the
existing `define macros.  `define macros already accept
almost any text as an argument.  To extend the behavior of
`define in a backwards-compatible manner you would need to
find some text to use as a macro argument that does not have
a valid meaning in standard verilog.

One way to avoid backward compatibility issues with macros
is to use a new definition syntax.  Verilog-compatible
macros are defined with `define.  New macros that allow for
named or defaulted arguments can be defined with a different
keyword, say `newdefine.  Then when the preprocessor sees
a macro reference like:

    `foo(.x(a), y(b))

it will decide how to expand it depending on whether foo was
defined with `define or `newdefine.  Presumably there will
be just one macro name space shared between `define and
`newdefine (or whatever we want to call it).

Paul