RE: [sv-bc] Mantis 1571: Add default values for macro arguments

I think that could be acceptable.

That would fit nicely with something else we want:

Today multi-line macros are written with \ at the end of each line,
which makes them ugly and difficult to read. 

An additional disadvantage is that you cannot nest multi-line macro
definitions. 
(It is not even clear that you can nest a single-line macro definition
within a multi-line macro definition, that is Mantis 1478, but let's
assume that it will be agreed that it is legal.)

So we want to have a macro definition syntax which has some sort of
begin-end delimiters, such as `begin_define - `end_define, for example.

That would allow macro definition nesting.

We could combine that with the capability of named argument association.


> One way to avoid backward compatibility issues with macros
> is to use a new definition syntax.  Verilog-compatible
> macros are defined with `define.  New macros that allow for
> named or defaulted arguments can be defined with a different
> keyword, say `newdefine.  Then when the preprocessor sees
> a macro reference like:
> 
>     `foo(.x(a), y(b))
> 
> it will decide how to expand it depending on whether foo was
> defined with `define or `newdefine.  Presumably there will
> be just one macro name space shared between `define and
> `newdefine (or whatever we want to call it).

Shalom