RE: [sv-bc] Mantis 1571: Add default values for macro arguments

I don't think this particular suggestion would work.

Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Paul Graham
> Sent: Friday, October 20, 2006 9:51 PM
> To: Greg Jaxon
> Cc: Bresticker, Shalom; Korchemny, Dmitry; Steven Sharp; SV_BC List
> Subject: Re: [sv-bc] Mantis 1571: Add default values for macro
arguments
> 
> This macro syntax is already legal in verilog-2001:
> 
>     `define ABC #(a, b, c)
> 
> I can also use the macro as:
> 
>     `ABC #(1, 2, 3)
> 
> Now this will result in illegal verilog:
> 
>     #(a, b, c) #(1, 2, 3)
> 
> but that is not an issue with the verilog macro language
> itself.  So do we want to extend the macro syntax in this
> way and rely on the semantics of verilog itself to avoid
> ambiguity?  (In the sense that conflicting interpretations
> of a macro expsnsion are not ambiguous if they both result
> in illegal verilog).
> 
> Paul