[sv-bc] FW: compiler directive with formal arguments

Re Mantis 1119, here is a user who does not want or expect arguments to
be expanded within regular quotes.

 

Shalom

 

________________________________

From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Marq Kole
Sent: Friday, November 03, 2006 2:58 PM
To: verilog-ams
Subject: compiler directive with formal arguments

 


All, 

At least one simulator has a different interpretation of a compiler
directive with formal arguments than any of the others (known to me) do.
Consider the macro definition: 

`define UPDATE_XML_ELEMENT(file,param,value,delta) \ 
if (delta) \ 
$fwrite(file, " <instance name=\"%M\">\n  <parameter name=\"%s\"
value=\"%1.8g\" delta=\"%1.8g\"/>\n </instance>\n", param, value,
delta); 

Now I would expect that a call 

`UPDATE_XML_ELEMENT(update_file, "vth0", Vth, -delta_vth) 

to be expanded to: 

if ( -delta_vth) \ 
$fwrite(update_file, " <instance name=\"%M\">\n  <parameter name=\"%s\"
value=\"%1.8g\" delta=\"%1.8g\"/>\n </instance>\n", "vth0", Vth,
-delta_vth); 

Instead this tool expands it to: 

if ( -delta_vth) \ 
$fwrite(update_file, " <instance name=\"%M\">\n  <parameter name=\"%s\"
Vth=\"%1.8g\"  -delta_vth=\"%1.8g\"/>\n </instance>\n", "vth0", Vth,
-delta_vth); 

So it replaces also the occurrences of "value" and "delta" inside the
format string of the $fwrite system task. 

The weird thing is that the LRM 2.2 standard according to section 11.3.1
only states that the scope of formal arguments extends to the end of the
line and that a formal argument can be used in the same manner as an
identifier. It nowhere exempts the contents of strings from formal
argument replacement. It is my feeling that this should be added to the
text. 

Then, on the other hand the text in 1364-2005 (section 19.3.1) is
exactly the same. Should we take the lead here? 


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors