Date: Mon Nov 27 2006 - 22:52:17 PST
Shalom, I think it would be a good idea to show us some of the design styles that would benefit from this feature. A feature is just one possible solution to a problem. There may be other ways of solving the problem, including use some existing features. However, it is difficult to design the feature without seeing the real problem. Unpacked arrays and arrays of interfaces could certainly solve the varying number of ports problem. Generic interfaces and parameterized types could potentially solve some of the conditional port problems as well. Dave ________________________________ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Bresticker, Shalom Sent: Monday, November 27, 2006 12:59 AM To: sv-bc@server.eda.org Subject: [sv-bc] Mantis 210: allow use of generate in port list Mantis 210 says, Some design styles at Freescale would benefit from the ability to include or not include ports on a module at elaboration time based on the value of a parameter or parameter override. Extending the generate construct to apply to port lists as well as module bodies seems like a good way to do this. Here's an example of what I'm proposing: module foo #(parameter flag=0) ( generate if (flag ==1) input x; endgenerate ); ... endmodule I did not submit Mantis 210. I think. To the best of my recollection, I did not even know about it. But I fully agree with the need. Both at Freescale and at Intel, the need for conditional (and multiple) ports has come up time and again. I'd like to solicit thoughts and suggestions that I can work up into a proposal. Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033
