Re: [sv-bc] non-existent ports or parameters

All of the situations that you have described should be considered
erroneous Verilog code.

Whether a tool produces an error, or tries to continue with a warning,
would be up to the implementation.  If the tool wants to provide a mode
that enforces strict compliance, then it would need to treat these as
errors in that mode.

Steven Sharp
sharp@cadence.com