Re: [sv-bc] Task and Function inout port with default argument

>From: Greg Jaxon <Greg.Jaxon@synopsys.com>

>I recall some extensive discussions of how to do
>name resolution in default value expressions.  These may have
>concluded that omitting actuals whose formals have "out" direction
>should update some default storage locations.
>That seems (just a bit) crazy to me, but if true it means my
>whole "cancel the copy-out" premise is wrong.

During those discussions, I expressed the opinion that copying to
some default storage location was weird.  However, since then I
have noticed an analogous situation where we do exactly that in
Verilog.

It occurs when the $random system function is called without a
so-called "seed" argument (actually the full state of the random
number generation stream, which is an inout).  The simulator uses
a hidden default storage location for the "seed" (actually state)
of the global random number generation stream.  It does both the
input and output side of the argument passing.

This is not actually a precedent for what we are talking about,
since this is a system function, not a Verilog function.  However,
it does illustrate a situation where an inout argument with a
default actual that copies in and out was useful.

Steven Sharp
sharp@cadence.com