[sv-bc] Agenda: SV-XC committee meeting (Dec 20, 2006)

-------- Original Message --------
Subject: FW: Agenda: SV-XC committee meeting (Dec 20, 2006)
Date: Tue, 19 Dec 2006 07:26:13 -0800
From: Logie Ramachandran <Logie.Ramachandran@synopsys.com>
To: Roy, Somdipta Basu <somdipta@ti.com>, Logie Ramachandran <Logie.Ramachandran@synopsys.com>, Ulrich Holtmann <Ulrich.Holtmann@synopsys.com>, Tapan Halder <Tapan.Halder@synopsys.com>,
shur@cadence.com, r.slater@freescale.com, arnab_saha@mentor.com, john_shields@mentor.com, akohli@cadence.com, mckinley@cadence.com, cranston@cadence.com, sv-xx@grfx.com, michaelw@cadence.com, Sudip
Chakrabarti <Sudip.Chakrabarti@synopsys.com>
CC: sv-ec@eda.org, sv-bc@eda.org, sv-cc@eda.org, sv-ac@eda.org, ieee1800@eda.org, Neil.Korpusik@Sun.COM, Karen Pieper <Karen.Pieper@synopsys.com>



-----Original Message-----
From: Logie Ramachandran
Sent: Sunday, December 17, 2006 9:27 AM
To: Roy, Somdipta Basu
Subject: Agenda: SV-XC committee meeting (Dec 20, 2006)

Hi All,

The next SV-XC committee is planned for Dec 20 2006.
Here are the details and agenda for the meeting.

Thanks

Logie

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SV-XC Committee Meeting
Date: Wednesday, December 20, 2006
Time: 8:00am-10:00am PST

Toll Free Dial In Number: (888)635-9997
International Access/Caller Paid Dial In Number: (763)315-6815
PARTICIPANT CODE: 564437


Agenda
------

+ Review IEEE patent policy

http://standards.ieee.org/board/pat/pat-slideset.ppt


+ Review minutes of the Dec 6, 2006 meeting (See attached)

+ Prioritization and schedule of the committee activities for 2007





SV-XC Committee Meeting
Date:    Wednesday, Dec 06, 2006
Time:    09:00am - 11:00 am PST

Attendees
------------------------------------------------
1
2
0
6
0
6
------------------------------------------------
p  Somdipta Roy (somdipta@ti.com
p  Logie Ramachandran (logie@synopsys.com)
p  Ulli Holtmann (ulrich@synopsys.com)
p  Tapan Halder (thalder@synopsys.com)
p  Bob Shur (shur@cadence.com)
p  Rob Slater (r.slater@freescale.com)
p  Arnab Saha (arnab_saha@mentor.com)
p  John Shields (john_shields@mentor.com)
p  Amit Kohli (akohli@cadence.com)
p  Kathy McKinley(mckinley@cadence.com)
p  Scott Cranston(cranston@cadence.com)
p  Kevin Camaron(sv-xx@grfx.com)
p  Michael Williams (michaelw@cadence.com)
p  Sudip Chakrabarti (sudip@synopsys.com)


Agenda

+ Review IEEE patent policy
http://standards.ieee.org/board/pat/pat-slideset.ppt

+ Reviewed the PAR
http://standards.ieee.org/board/nes/projects/1800.pdf

+ Scope of Work
Committee brainstormed on important topics of interest

                  SystemC
                  -------
-  Extension of DPI for SystemC (Arnab)
-  SV extensions to support general C++ [DPI-C++] (Kevin)
-  Consistent scheduling semantics between SystemC and SystemVerilog
-  Delta cycle semantics between SystemC and SystemVerilog
-  Instantiation of SystemC module inside Verilog and vice-versa
-  Out of module references between SystemC and Verilog
-  Event semantics across SystemC and SystemVerilog (Rob)
   (i.e, waiting for an event from the other language)
-  Net connections traversing language boundary 
-  Accessing SystemC class objects from SystemVerilog (Kevin)


                    VHDL
                    ----

-  Referencing objects from other SV (Kathy)
-  Type of objects that can be connected together
   (e.g.,  SystemVerilog net to VHDL variable?)
-  Network resolution between SystemVerilog and VHDL (Kathy)
-  Multiple drivers from multiple languages 
-  User defined resolutions across multiple languages
-  complex data types across language boundary
-  parameters or generic type overrides
-  timescale across Verilog and VHDL
-  cross language instantiation
-  library handling (order of scanning libraries)
-  case sensitivity
-  Port directions: While VHDL/SystemC have stricter port
   direction rules, Verilog port direction is more like
   a comment and simulators coerce the directions based
   on usage
-  VPI/VHPI across the languages


AMS
---
-  Conflict with logic keyword (Tapan)
-  Proposal for integrating Verilog AMS into SystemVerilog (Kevin)
-  Force/release semantics on mixed net
-  Data types allowed on mixed nets


General issues
--------------
-  Will this committee's work result in a dot standard. Committee
   felt that the dot standard gives us more flexibility in 
   terms of release schedule. Some members felt it was too early
   to decide on this issue. 
-  Committee to recommend changes to AMS/VHDL/SystemC standards
   as appropriate
-  Interface to emulators (SCEMI interface between TB and emulator)



+ Prioritization of issues

Committee members felt that the issues should be broadly classified
into 2 buckets (1) elaboration issues and (2) runtime issues. 
Prioritization between these buckets were discussed and it was
felt that elaboration issues should be tackled first. 

Approach would be to work together in a single group to come up with
common definitions of drivers and nets.  Then subgroups can look
at language specific issues in VHDL, SystemC and AMS

Get broad requirements from user community (John Shields).

+ Meeting Frequency

Committee will meet once every 2 weeks. Wednesday morning
8AM-10AM PST.  
 

Action Items
- Logie and Somdipta to collect user requirements from the broad
  user community
- Logie to setup website and email for committee
- Somdipta and Rob Slater  to collect prioritization of issues
  from their respective companies.