Re: [sv-bc] When are constant expressions evaluated?

   Should the same principles of "static type-correctness" apply also to
   parameter, parameter types and parameter expressions, as they
   do to ordinary identifiers, types and expressions?

   Nikhil

   Bresticker, Shalom wrote:

 Yulik Feldman pointed out the same idea.

 What prompted this question was the following example from 20.4.4:

 interface intf_t #(num_clients = 0);
 bit [num_clients-1:0] req;
 for (genvar i=0; i< num_clients; i++) begin: mps
 modport client_mp (output .client_req( req[i] ));
 end
 endinterface

 This example has two oddities:

 1. For num_clients = 0 (default), the bit-range of req is defined with
 MSB < LSB, whereas for normal values MSB >= LSB. I.e., the direction of
 the bit-range is different.

 2. For num_clients = 0, the generate for-loop is an infinite loop:

 for (genvar i=0; i< 0; i++)

 Shalom


  

 I think there was someone using Verilog-AMS who wanted to make
 a parameter mandatory (ie, you must specify it) and thus gave
 an illegal default.  However, in this case, he was using the
 "ranges" allowed in AMS paramter declarations:

 parameter real myparm = -1 from (0:inf);

 where (0:inf) means that only positive values are allowed.
    

  

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.