Date: Tue Feb 20 2007 - 00:16:06 PST
________________________________ <http://as.cmpnet.com/event.ng/Type=click&FlightID=75634&AdID=125682&Tar getID=2625&Segments=1411,3108,3448,8796&Targets=2625,2878,6521&Values=34 ,46,51,63,77,82,93,100,140,304,309,442,450,646,1184,1255,1388,1405,1430, 1766,1785,1798,1925,2299,2326,2678,2727,2895,3216,3224,3347,4079&RawValu es=IP,66.77.24.210,&Redirect=http://www.cmp.com> <http://as.cmpnet.com/event.ng/Type=count&ClientType=2&AdID=125682&Fligh tID=75634&TargetID=2625&Segments=1411,3108,3448,8796&Targets=2625,2878,6 521&Values=34,46,51,63,77,82,93,100,140,304,309,442,450,646,1184,1255,13 88,1405,1430,1766,1785,1798,1925,2299,2326,2678,2727,2895,3216,3224,3347 ,4079&RawValues=&random=cahixiw,bcKvlqcbnqbzj> <http://as.cmpnet.com/event.ng/Type=click&FlightID=76830&AdID=127621&Tar getID=4227&Segments=823,885,1411,2722,3108,3448,3598,5064,7626&Targets=6 49,786,2625,2878,4227&Values=34,46,51,63,77,82,93,100,140,203,304,309,44 2,450,646,1184,1255,1388,1405,1430,1766,1785,1798,1925,2299,2326,2678,27 27,2895,3347,4079&RawValues=IP,66.77.24.210,&Redirect=http://www.magma-d a.com/MUSIC.html> <http://as.cmpnet.com/event.ng/Type=count&ClientType=2&AdID=127621&Fligh tID=76830&TargetID=4227&Segments=823,885,1411,2722,3108,3448,3598,5064,7 626&Targets=649,786,2625,2878,4227&Values=34,46,51,63,77,82,93,100,140,2 03,304,309,442,450,646,1184,1255,1388,1405,1430,1766,1785,1798,1925,2299 ,2326,2678,2727,2895,3347,4079&RawValues=&random=chjyyIn,bcKvlqcbjmlyW> <http://www.cmp.com/> <http://www.eetimes.com/> EE Times <http://www.eetimes.com/> : Design News <http://www.eetimes.com/news/design/> SysVerilog support falls short for design Richard Goering <mailto:rgoering@cmp.com> (02/19/2007 9:00 AM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=197006799 Santa Cruz, Calif. -- A full-court marketing push by major EDA vendors on behalf of the SystemVerilog language is working--but not as expected. Although the unified design and verification language is widely applied to verification, design use lags because of concerns about tool support. SystemVerilog adds assertions, testbench generation and design language constructs to Verilog, the most widely used hardware description language (HDL) for IC design. EDA vendor investment in SystemVerilog, which became the IEEE <http://www.eetimes.com/encyclopedia/defineterm.jhtml?term=IEEE&x=&y=> 1800 standard in late 2005, is huge. According to the Accellera standards organization, this year 136 vendors will offer more than 350 SystemVerilog products, compared with six vendors and nine products in 2004, when SystemVerilog 3.1a became an Accellera standard. Estimates of the number of Verilog users who have stepped up to SystemVerilog range anywhere from 20 to 50 percent, but one point of agreement is that the most commonly used SystemVerilog feature is assertions. Next comes testbench constructs. Falling well behind is design, where SystemVerilog adds a number of constructs that let designers work at a higher level of abstraction. Adoption of the design feature, however, has been hampered by the less than 100 percent language support for those constructs. "I thought designers would pick it up first, but they're a little more cautious about it," said Cliff Cummings, president of the training firm Sunburst Design Inc. and a contributor to SystemVerilog. Verification engineers, he conceded, need only a simulator to use SystemVerilog, while designers require synthesis, simulation and linting tools. "On the design side, several tools are involved, and they all have to support the same SystemVerilog constructs for you to use them," said Stu Sutherland, president of training firm Sutherland HDL. "Today, different tools have implemented different portions of SystemVerilog, so it's very hard to do design." While the primary usage of SystemVerilog today is assertions, it's actually the hardest part of SystemVerilog to learn because it involves a specialized assertion language, Sutherland said. Design constructs, on the other hand, have a "very minimal" learning curve, he said. Analyst Gary Smith, president of Gary Smith EDA, estimates that SystemVerilog pen- etration is about 35 percent. "The overwhelming reason for adoption is its assertions capability," he said. SystemVerilog is supplanting Synopsys Inc.'s Vera verification language, but not Cadence Design Systems Inc.'s "e," which Smith views as a higher-level language. SystemVerilog in use At the Design and Verification Conference (DVCon) in San Jose, Calif., this week, Stefan Sandstrom, ASIC <http://www.eetimes.com/encyclopedia/defineterm.jhtml?term=ASIC&x=&y=> systems architect at Axis Communications <http://www.eetimes.com/encyclopedia/defineterm.jhtml?term=Communication s&x=&y=> AB (Sweden), will describe his company's use of SystemVerilog for the design of a 3 million-gate system-on-chip. This effort used SystemVerilog for design and assertions, but not testbench generation, Sandstrom said. SystemVerilog assertions help engineers find bugs faster and more easily, assist the documentation of intended behavior and increase the quality of RTL code, he said. "Assertions are trickier to learn, at least initially. They have a very compact syntax, and they require a new way of thinking about the design," Sandstrom noted. SystemVerilog design constructs such as interfaces and extended data types are also helpful, he said, while SystemVerilog synthesis is working well. Learning the language isn't hard, said Sandstrom, but the challenge is figuring out what works best in practice. "There are still quite a few holes in tool support, especially for simulation," he warned. "When you're trying out fancy combinations of language features, it's still likely you'll get a 'not implemented yet' error message. You should probably stick to standard ways of doing things." Sameer Goyal, principal engineer at Exar Corp., is using SystemVerilog for its testbench constructs, but he has made only minimal use of assertions. Testbench features like built-in randomization, which allows constrained- random testing, have boosted verification productivity by a factor of three over plain Verilog, Goyal said. Exar also uses SystemVerilog's functional coverage capability. Exar doesn't use assertions often, "because we don't have the resources to really dig deep into that. It's learning a new language," Goyal said. Exar also isn't using SystemVerilog for design. "There's some hesitancy there in terms of what the tools support and what they can or cannot do," he said. At DVCon, Bill Dittenhofer, a development engineer at Hewlett-Packard Co.'s System VLSI Lab, will share his experiences with SystemVerilog and SystemC at his former employer, Starkey Laboratories. "We started to use some of the SystemVerilog features for verification in lieu of some of the stuff in SystemC," he said. "We used SystemC to do very high-level modeling, and the two of them interacted quite well." Dittenhofer said that SystemVerilog design constructs such as interfaces, structures, packages, classes and enumerated types are helpful, but didn't get much use at Starkey. "At the time, they really weren't supported by synthesis vendors." SystemVerilog tools, he said, "have had some teething problems." A push for adoption Most indications point to a fairly rapid adoption for SystemVerilog. In the EE Times 2006 EDA Users Survey, 35 percent of North American ASIC designers said they were using the language now, and an additional 34 percent expected to use it in two years. In Asia, the figures were 41 and 38 percent respectively. More than half of those attending the Synopsys Users Group last year said they were using SystemVerilog assertions today, and 75 percent planned to use them within 12 months, said Swami Venkat, senior director of marketing for Synopsys' verification group. Ten percent said they were using SystemVerilog for design. Cadence now has some 150 customers using SystemVerilog, said Steve Glaser, corporate vice president for the verification division. A Cadence survey found that 57 percent are using design constructs, 60 percent assertions and 57 percent testbench constructs. However, Glaser said, "the primary use of all constructs that cross the design and verification boundaries is in verification." A company seeing far less SystemVerilog usage is FPGA synthesis provider Synplicity. In a 2005 survey, only 2 percent of customers said they were using SystemVerilog, with 17 percent planning to do so in two years, said Jeff Garrison, director of inbound marketing. Mentor Graphics' Questa simulation platform <http://www.eetimes.com/encyclopedia/defineterm.jhtml?term=platform&x=&y => supports about 95 percent of the language, said John Lenyo, director of marketing for verification and test. Cadence "now supports all language constructs required for both design team and advanced verification team methodologies," said Glaser. Synopsys "supports most of SystemVerilog today, and is rapidly adding support for new constructs based on customer requests," said Venkat. What's really needed, said Sutherland, is an "interoperability checklist" that identifies stages of support for SystemVerilog constructs. If a given set of tools has support up to "stage five," for instance, users will know they can safely use "stage five" constructs with all those tools. "All tools should support 100 percent of the language, but nobody can get there instantly," Sutherland said. All material on this site Copyright (c) 2007 CMP Media LLC <http://www.cmp.com/delivery/copyright.html> . All rights reserved. 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