[Yulik] > I would like to propose to make part selects operators and > to allow them to select parts of arbitrary expressions. I think this leads to many difficulties. Verilog vector subscripts can have ascending or descending ranges, and need not be based at 0. To allow subscripting of expressions we must make a decision about the subscript bouunds of the expression. For example, what happens here? logic [1:15] a; logic [2:5] b; $display( {a, b}[5:2] ); It's worth noting that VHDL got itself into quite serious trouble over exactly this issue (subscript range of a concatenation). The only reasonable answer is to give the expression a self-determined range such as [N-1:0]. But that would cause further trouble. Given the definition of 'a' above, it's clear that a[3:0] is illegal. But what about (a)[3:0] ?? Is (a) an expression, or merely a syntactic wrapper for the variable a? It would be very confusing for them to be different. Given all of this, I think that the existing requirement to use a temporary variable (or an alias) is entirely reasonable and is not a serious limitation. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Feb 20 07:40:05 2007
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