RE: [sv-bc] part selects on arbitrary expressions

IMHO, defining operands of part select operator as self-determined will
make the construct expectable enough.

--Yulik.

-----Original Message-----
From: Gordon Vreugdenhil [mailto:gordonv@model.com] 
Sent: Tuesday, February 20, 2007 5:52 PM
To: Bresticker, Shalom
Cc: Feldman, Yulik; sv-bc@server.eda.org
Subject: Re: [sv-bc] part selects on arbitrary expressions

I would likely be even more hesitant to limit such expressions
with semantic rules that depend on expectations of "well behaved"
expressions.  Users are often surprised about how Verilog
expressions are typed (particularly people coming into SV
testbench coding from C/C++ backgrounds) and having constructs
that don't compose in a regular manner would not be good.

Gord.

Bresticker, Shalom wrote:
> One alternative might be to define a partial solution which would be
> well-defined and still give a solution for a large percentage of the
> cases.
> 
> Shalom
> 
>> -----Original Message-----
>> From: Gordon Vreugdenhil [mailto:gordonv@model.com]
>> Sent: Tuesday, February 20, 2007 5:23 PM
>> To: Bresticker, Shalom
>> Cc: Feldman, Yulik; sv-bc@server.eda.org
>> Subject: Re: [sv-bc] part selects on arbitrary expressions
>>
>> My concerns would be that unless you make the expression on which
>> the select operates a self-determined expression, the behavior
>> is going to be, perhaps, surprising.  If you do make it self
>> determined, it might be even more surprising since the
>> equivalent behavior that Yulik appears to want would not necessarily
>> hold.  I suspect that there are some surprising edge cases
>> in either choice which makes me pretty hesitant to do this.
>>
>> Gord.

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com

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