RE: [sv-bc] implicit net declarations on ports

Stu,

> I like Shalom's suggestion.  Syntactically, it would be easy to add a
> "ports_only" or similar argument to `default_nettype.  This feature
> would be
> a very useful compromise between the convenience of inferred nets and
> the
> risks of unintentionally inferred nets.
> 
> A semantic change is required for this enhancement.  Currently, any
> `default_nettype overrides any previously specified `default_nettype
> directive.  For "`default_nettype ports_only", it should just modify
any
> previous directive.  So, for example, I should be able to do:
> 
>   `default_nettype pull1
>   `default_nettype ports_only
>    module foo (input [7:0] a, output [7:0] b);
>    ...

[SB] I think it might be simpler to have 'ports_only' on the same line
as the other argument and continue to have it override the last
`default_nettype directive.

The current syntax is

default_nettype_compiler_directive ::=
                                  `default_nettype default_nettype_value

I would change this to

default_nettype_compiler_directive ::=
                   `default_nettype [ ports_only ] default_nettype_value

I'll file a Mantis.

> Taking this one step further, I think this extension would become even
> more
> useful if it also modified the .name and .* constructs, which
currently
> require explicit net (or variable) declarations.  The rule should be
> added
> that a net inferred from an explicitly named module port will be
> connected
> to port instances of the same name, provided all rules for the
inferred
> connection are met.
> 
> This, however, would be a bigger change, and might have backward
> compatibility issues.  Currently implicit nets are NOT inferred from
> port
> declarations, but from port instance connections (or the LHS of
> continuous
> assigns).  Since .* and .name do not explicitly name a signal, no net
is
> inferred, even when the identifier is in the containing module's port
> list.

[SB] I'm not sure what you mean. Do you mean that .name and .* do not
connect to previously implicitly declared nets and you want them to, or
do you mean that they do not create implicit net declarations and you
want to allow them to? 

It is of course true that they do not create implicit net declarations.
However, the LRM does not say, as far as I see, that they do not connect
to previously implicitly declared nets. In fact, two simulators I tested
do so connect.

Example:

module top(input w, output o);
m m(.*);
endmodule

module m(input w, output o);
endmodule

This works fine. A clarification in the LRM might be desirable.

Note: The LRM is unclear what happens if you do .name or .* to a net
which does not clear. The LRM only says that an implicit net declaration
is not created. It does not say whether this leaves the port
unconnected, generates a warning, or generates an error. This is Mantis
1660.

Shalom

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