RE: [sv-bc] part selects on arbitrary expressions

However, it would be necessary to define whether bit-sizing and
bit-extension are performed before the indexing or after.

Shalom

> -----Original Message-----
> From: Bresticker, Shalom
> Sent: Sunday, February 25, 2007 9:39 AM
> To: Korchemny, Dmitry; sv-bc@server.eda.org
> Subject: RE: [sv-bc] part selects on arbitrary expressions
> 
> A syntax like $expr(a+b)[3:0] might be slightly more intuitive.
> 
> Shalom
> 
> > -----Original Message-----
> > From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
> On
> > Behalf Of Korchemny, Dmitry
> > Sent: Tuesday, February 20, 2007 7:12 PM
> > To: Jonathan Bromley; Feldman, Yulik; sv-bc@server.eda.org
> > Subject: RE: [sv-bc] part selects on arbitrary expressions
> >
> > Hi all,
> >
> > This problem may be overcome if a new syntax is introduced: e.g.,
> > instead of $subvec(a, 3, 0) instead of (a)[3:0].
> >
> > I would also like to mention that part select is important for
writing
> > assertions. Using a straightforward syntax causes semantic or
> syntactic
> > problems, as in the following example:
> >
> > property p(x, y);
> >    x[0] |-> y;
> > edproperty
> >
> > assert property (p(a[2], b));
> >
> > Writing it as
> >
> > property p(x, y);
> >    $subvec(x, 0, 0) |-> y;
> > endproperty
> >
> > will do the work.
> >
> > Thanks,
> > Dmitry
> >
> > -----Original Message-----
> > From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
> On
> > Behalf Of Jonathan Bromley
> > Sent: Tuesday, February 20, 2007 5:34 PM
> > To: Feldman, Yulik; sv-bc@server.eda.org
> > Subject: RE: [sv-bc] part selects on arbitrary expressions
> >
> > [Yulik]
> > > I would like to propose to make part selects operators and
> > > to allow them to select parts of arbitrary expressions.
> >
> > I think this leads to many difficulties.
> >
> > Verilog vector subscripts can have ascending or descending
> > ranges, and need not be based at 0.  To allow subscripting
> > of expressions we must make a decision about the subscript
> > bouunds of the expression.
> >
> > For example, what happens here?
> >
> > logic [1:15] a; logic [2:5] b;
> > $display( {a, b}[5:2] );
> >
> > It's worth noting that VHDL got itself into quite serious
> > trouble over exactly this issue (subscript range of a
> > concatenation).
> >
> > The only reasonable answer is to give the expression a
> > self-determined range such as [N-1:0].  But that would
> > cause further trouble.  Given the definition of 'a' above,
> > it's clear that
> >
> >   a[3:0]
> >
> > is illegal.  But what about
> >
> >   (a)[3:0]
> >
> > ?? Is (a) an expression, or merely a syntactic wrapper
> > for the variable a?  It would be very confusing for them
> > to be different.
> >
> > Given all of this, I think that the existing requirement
> > to use a temporary variable (or an alias) is entirely
> > reasonable and is not a serious limitation.
> > --
> > Jonathan Bromley, Consultant
> >
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
> >
> > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
> > 1AW, UK
> > Tel: +44 (0)1425 471223                   Email:
> > jonathan.bromley@doulos.com
> > Fax: +44 (0)1425 471573                           Web:
> > http://www.doulos.com
> >
> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.
> >
> > --
> > This message has been scanned for viruses and
> > dangerous content by MailScanner, and is
> > believed to be clean.
> >
> > --
> > This message has been scanned for viruses and
> > dangerous content by MailScanner, and is
> > believed to be clean.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.