Re: [sv-bc] Are modport port directions enforced?

According to 20.4

"To restrict interface access within a module, there are modport lists
with directions declared within the interface. The keyword modport
indicates that the directions are declared as if inside the module."

-- Brad


________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Francoise Martinolle
Sent: Monday, February 26, 2007 1:19 PM
To: Mark Hartoog; sv-bc@eda-stds.org
Subject: RE: [sv-bc] Are modport port directions enforced?


Where is the LRM text supporting your answer?


________________________________

	From: Mark Hartoog [mailto:Mark.Hartoog@synopsys.com] 
	Sent: Monday, February 26, 2007 4:17 PM
	To: Francoise Martinolle; sv-bc@eda-stds.org
	Subject: RE: [sv-bc] Are modport port directions enforced?
	
	
	If it is a variable, as in your example, it should be an error.
If it is a net, then you might argue it should be allowed.


________________________________

		From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]
On Behalf Of Francoise Martinolle
		Sent: Monday, February 26, 2007 1:08 PM
		To: sv-bc@eda-stds.org
		Subject: [sv-bc] Are modport port directions enforced?
		
		
		I have a question regarding the modport port directions.
		If I declare a modport port in an interface with
direction input, should it be an error
		if the module which uses this modport tries to assign to
the modport port of direction input?
		 
		I cannot find anything in the LRM which talks about
modport port direction enforcements.
				interface data_if ();
		 
		logic [31:0] d;
		 
		modport in  (input d);
		
		modport out (output d);
		 
		endinterface: data_if
		 
				module duv (data_if.in i, data_if.out
o);
		 
		assign i.d = o.d;     ====> is this allowed?
		 
		endmodule: duv
		 
		endinterface: data_if

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