RE: [sv-bc] Are modport port directions enforced?

There is no continuous assignment to the whole interface, but there is a
continuous assignment to the variables/nets that the modport makes input
ports. If you do not have a modport, then the variables would be ref
ports, and there would be no continuous assignment. 


________________________________

	From: Francoise Martinolle [mailto:fm@cadence.com] 
	Sent: Monday, February 26, 2007 1:35 PM
	To: Mark Hartoog; sv-bc@eda-stds.org
	Subject: RE: [sv-bc] Are modport port directions enforced?
	
	
	Mark,
	 
	The modport port is what is connected to the port named "i" of
the module duv. The port named "i"
	has no explicit direction. Furthermore a modport can be a
collection of ports, one may be input, the other output, another inout.
	I do not see how you can apply the rule of a single assignment
to a variable in my example.
	There is no continuous assignment to the modport "in" of the
module duv.
	 
	Francoise
	       '
	
	

________________________________

		From: Mark Hartoog [mailto:Mark.Hartoog@synopsys.com] 
		Sent: Monday, February 26, 2007 4:30 PM
		To: Francoise Martinolle; Mark Hartoog;
sv-bc@eda-stds.org
		Subject: RE: [sv-bc] Are modport port directions
enforced?
		
		
		When you instantiate the module, there is an implicit
continuous assignment to the input port. If there is another continuous
or procedural assignment inside the module to the port, then that
violates the one continuous assignment or one or more procedural
assignment rules for variables. This is covered in section 6.7 and 11.5.


________________________________

			From: Francoise Martinolle
[mailto:fm@cadence.com] 
			Sent: Monday, February 26, 2007 1:19 PM
			To: Mark Hartoog; sv-bc@eda-stds.org
			Subject: RE: [sv-bc] Are modport port directions
enforced?
			
			
			Where is the LRM text supporting your answer?


________________________________

				From: Mark Hartoog
[mailto:Mark.Hartoog@synopsys.com] 
				Sent: Monday, February 26, 2007 4:17 PM
				To: Francoise Martinolle;
sv-bc@eda-stds.org
				Subject: RE: [sv-bc] Are modport port
directions enforced?
				
				
				If it is a variable, as in your example,
it should be an error. If it is a net, then you might argue it should be
allowed.


________________________________

				From: owner-sv-bc@eda.org
[mailto:owner-sv-bc@eda.org] On Behalf Of Francoise Martinolle
				Sent: Monday, February 26, 2007 1:08 PM
				To: sv-bc@eda-stds.org
				Subject: [sv-bc] Are modport port
directions enforced?
				
				
				I have a question regarding the modport
port directions.
				If I declare a modport port in an
interface with direction input, should it be an error
				if the module which uses this modport
tries to assign to the modport port of direction input?
				 
				I cannot find anything in the LRM which
talks about modport port direction enforcements.
				
				interface data_if ();
				 
				logic [31:0] d;
				 
				modport in  (input d);
				
				modport out (output d);
				 
				endinterface: data_if
				 
				module duv (data_if.in i, data_if.out
o);
				 
				assign i.d = o.d;     ====> is this
allowed?
				 
				endmodule: duv
				 
				endinterface: data_if

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