RE: [sv-bc] Are modport port directions enforced?

> For example, you can have tasks in interfaces that are used 
> to access the objects in the interface.  These tasks can be 
> called from different modules where the interface has been 
> passed.  If passing the interface is making copies of the 
> objects in the interface, then which object is the task 
> supposed to access?  Does it access the copy that is visible 
> to the module doing the call?  I am not sure how that would 
> be implemented, and it probably wouldn't have the expected 
> behavior.  

Consider this case:

module interf;
integer x;
task print();
  $display("x = ", x);
endtask
endmodule

module child(output integer o);
initial
begin
   o = 5;
   top.interf.print();
end
endmodule

module top;
interf interf();
child child(interf.x);
endmodule

What value will this print? Are there Verilog simulators where this
will not print '5'?


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