RE: [sv-bc] Function return values

Jonathan,

The two mechanisms ought to be completely equivalent. Hence, a return
statement must update the variable associated with the function name,
just like the assignment form.

	Arturo

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Jonathan Bromley
Sent: Thursday, March 01, 2007 2:00 AM
To: sv-bc@eda-stds.org
Subject: [sv-bc] Function return values

SV-BC,

Please accept my apologies if this has already been answered.

In SystemVerilog we have two different ways to return values 
from a function:

<function_name> = <expression>;
return <expression>;

As far as I can see, both methods can coexist in the same 
function.  This yields an ambiguity for static functions.
Does the "return <expression>;" form also, as a side-effect,
update the <function_name> variable?  Consider the following:

module M;  // functions in a module are static by default
  function int F(input bit B, input int I);
    if (B) return I;
  endfunction : F
  initial begin
    $display(F(0,3));   // displays '0'
    $display(F(1,5));   // obviously displays '5'
    $display(F(0,0));   // displays ?????
  end
endmodule : M

My understanding is that the implicit function_name variable
'F' is initialised to 0 like any int, hence the function's
return value in the first call is reliably 0.  But the second
call executes a return statement.  Does this, or does it not,
update F and thereby influence the result of the third call?

Thanks
-- 
Jonathan Bromley, Consultant

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