[sv-bc] initial values in VCD

<forwarding email from Doron Bustan>

-------- Original Message --------
Date: Thu, 01 Mar 2007 11:17:19 -0600
From: Doron Bustan <dbustan@freescale.com>
To: sv-ec@server.eda.org, sv-cc@server.eda.org
CC: John Havlicek <john.havlicek@freescale.com>,
        Fais Yaniv-RM96496 <Yaniv.Fais@freescale.com>
Subject: initial values in VCD

Hi all,

I hope that I am addressing the right forum.

I think that the VCD section of the LRM should define the dumping of
initial values of variables.
In 1800 LRM there is a change in the scheduling semantics for initial
assignment of the form "int i = 3;".
Section 6.4 of 1800 says:

"In Verilog, an initialization value specified as part of the
declaration is executed as if the assignment were
made from an initial block, after simulation has started. In
SystemVerilog, setting the initial value of a
static variable as part of the variable declaration (including static
class members) shall occur before any
initial or always blocks are started."

Section 18.1.3 of 1364 says
"Executing the $dumpvars task causes the value change dumping to start
at the end of the current simulation
time unit."

This means that initial values should not be dumped before the first
time step, and thus, any initial value
that is bing overridden at an initial block, cannot be seen in a wave
form. I think that it would be useful to be
able to see these values, thus there should be a change for the semantics.

What do you think?
I guess that I need to put a mantis item for this. Which committee
should handle this?

Thanks

Doron



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