RE: [sv-bc] part selects on arbitrary expressions

Maybe the LRM should define what "compile time" means.  Does it mean
"before the big bang of simulation"? (That phrase is from
http://www.eda.org/sv-bc/hm/2580.html .)

Regarding x's, a macro could be based on a >>> shift of

    $signed({1'bx,expr})

which shifts in x's.

However, before I could believe that such a macro is easy, I'd need to
see a worked out one that takes into account all possible ranges.  The
type of an expression could be downto or "upto" and with one bound
negative and the other positive.  A general macro would seem to need
$left, $right, and $increment, as in

    http://www.eda-stds.org/sv-bc/hm/2796.html 

Another thread about these kinds of tricks was

    http://www.eda-stds.org/sv-bc/hm/4870.html 

-- Brad


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven Sharp
Sent: Tuesday, March 06, 2007 5:50 PM
To: sharp@cadence.com; Greg.Jaxon@synopsys.COM
Cc: yulik.feldman@intel.com; sv-bc@eda.org
Subject: Re: [sv-bc] part selects on arbitrary expressions


>From: Greg Jaxon <Greg.Jaxon@synopsys.com>

>> Is there any reason this functionality cannot be obtained via a shift

>> right, followed by a cast to the desired width?
>
>Out-of-bounds part selects produce Xs whereas shift and cast bring in 
>sign bits
and/or 0s.

You have a good point that this is a distinction between the two.

However, an out of bounds part select is also allowed to produce a
compile error.  So a design cannot be written to rely on this X
behavior.  For any valid design written with a part select (i.e.
one that is guaranteed to compile without error), the shift and cast
would still produce the same result.

Steven Sharp
sharp@cadence.com


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