RE: [sv-bc] part selects on arbitrary expressions

Steven Sharp once pointed out the following:
 
"Making bit and part selects operators that can act on any vector value
would also allow some strange syntax. Since the result of a bit or part
select is a vector, there would be nothing to prevent taking another bit
or part select of that result. That would allow things like r[i][j][k],
which might look like a reference to a multidimensional array, but is
just a bit-select of a bit-select of a bit-select. Or it would allow
things like r[7:0][6:0] or r[7:0][3], which look like some kind of array
slicing that isn't legal in Verilog, but are just further selects of the
result of a part select. You could even use r[i][3:0], which looks like
a part select of an array reference, but is actually a part select of a
bit select, with all but one of the selected bits out of range.

This means that if you put too many subscripts on your array reference,
your tool wouldn't give you an error message any more. This is already
an issue with allowing bit selects of array elements, since one too many
subscripts will be treated as a bit select. But this would allow an
arbitrary number of excess subscripts without any error."

Shalom

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