RE: [sv-bc] part selects on arbitrary expressions

Well,

1. It is not clear until it is clearly specified by the LRM.
2. It is not clear to me.
3. I'm not sure the LRM is full of such examples (selecting one element
of an unpacked array and assigning it in a questionable context). At
least I can not quickly find such an example.

--Yulik.

-----Original Message-----
From: Bresticker, Shalom 
Sent: Sunday, March 11, 2007 5:10 PM
To: Feldman, Yulik
Cc: 'sv-bc@server.eda.org'
Subject: RE: [sv-bc] part selects on arbitrary expressions

I repeat, you have always been able to do this. It is clear that the
selection of a single element of an array is the type of the element.
The LRMs are full of this.

Shalom

> -----Original Message-----
> From: Feldman, Yulik
> Sent: Sunday, March 11, 2007 5:07 PM
> To: Bresticker, Shalom
> Cc: 'sv-bc@server.eda.org'
> Subject: RE: [sv-bc] part selects on arbitrary expressions
> 
> Note that "b" is an unpacked array. A one-element unpacked array is
> not assignment compatible to the type of the element of the array. The
> question is whether the type of "b[0]" and "b[0:0]" is a one-element
> unpacked array or the type of the element itself.
> 
> --Yulik.
> 
> -----Original Message-----
> From: Bresticker, Shalom
> Sent: Sunday, March 11, 2007 4:51 PM
> To: Feldman, Yulik
> Cc: 'sv-bc@server.eda.org'
> Subject: RE: [sv-bc] part selects on arbitrary expressions
> 
> These have always been legal, even in Verilog-1995. Just replace 'bit'
> by 'reg'.
> 
> > bit a;
> > bit b [1:0];
> > assign a = b[0];
> >
> > A similar issue is with part selects, selecting one element only:
> >
> > assign a = b[0:0];

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