RE: [sv-bc] part selects on arbitrary expressions

From: Feldman, Yulik <yulik.feldman_at_.....>
Date: Mon Mar 12 2007 - 07:16:00 PDT
Not exactly. Maybe the confusion comes from the fact that I used the
term "operand" in a different meaning than it used in the LRM. Whenever
I used the term "operand" I meant "an expression on which the operator
operates", not the "leaf" expression, as defined by LRM. I find LRM's
definition of this term quite confusing due to the fact that the other
definition is very common. If this is indeed what caused your
misunderstanding of what I wrote, then first, I apologize, and second,
try to re-read the text considering the above definition of the term
"operand".

 

If this not the problem, then I'll try to elaborate:

 

By "context-determined" I meant exactly the same definition as in 1364
5.4.1 "Rules for expression bit length": 

 

"A context-determined expression is one where the bit length of the
expression is determined by the bit length of the expression and by the
fact that it is part of another expression. For example, the bit size of
the righthand side expression of an assignment depends on itself and the
size of the left-hand side."

 

I.e., the type of the operand of the parenthesis (I continue to use the
same meaning of "operand" term that used before) is influenced not only
by types of expressions within the sub-tree of this operand, but also by
types of expressions part of which the parenthesis operator is.

 

However, since in the specific example we're discussing the parenthesis
is found in self-determined context of the part select, the types of
parent expressions of part select do not influence the parenthesis, and,
consequently, the operand of the parenthesis. So, in this example, the
meaning of "context-determined" and "self-determined" for the operand of
parenthesis are practically the same. But, formally, the operand of
parenthesis should be always treated as context-determined and the
operand of part select should be always treated as self-determined.

 

--Yulik.

 

________________________________

From: Bresticker, Shalom 
Sent: Monday, March 12, 2007 3:30 PM
To: Feldman, Yulik; 'sv-bc@server.eda.org'
Subject: RE: [sv-bc] part selects on arbitrary expressions

 

When you write that the 'operand of the parentheses is
context-determined', do you mean that the expression within the
parentheses is context-determined in the sense that the types of the
operands inside are influenced by the other operands within the
parentheses? 

 

Shalom

 

________________________________

From: Feldman, Yulik 
Sent: Sunday, March 11, 2007 6:27 PM
To: Bresticker, Shalom; 'sv-bc@server.eda.org'
Subject: RE: [sv-bc] part selects on arbitrary expressions

 

Probably I was not clear enough; I hoped the previous discussion made it
clear. 

 

If we consider the parenthesis as a fully syntactic sugaring (which it
is), then we have only two expressions: the part select operator and its
operand. This operand is always self-determined and this is the end of
the definition.

 

If we consider the parenthesis as a kind of "identity" operator, then we
have three expressions: the part select operator, the parenthesis
operator (which is the operand of the part select) and the selected
expression (which is the operand of the parenthesis). The operand of the
part select is always self-determined and the operand of the parenthesis
is always context-determined. This definition is semantically equivalent
to the previous definition, w.r.t. to the inferred types. So, it doesn't
matter how you look on it, the operand of the part select is (should be)
always self-determined, and the "operand" of the parenthesis "operator"
should be context-determined (if you choose to treat the parenthesis as
an operator).

 

--Yulik.

 

________________________________

From: Bresticker, Shalom 
Sent: Sunday, March 11, 2007 5:40 PM
To: Feldman, Yulik; sv-bc@server.eda.org
Subject: RE: [sv-bc] part selects on arbitrary expressions

 

I think those last two bullets are contradictory.

 

Shalom

 

*  The parenthesis "()" in Verilog is a kind of syntactic sugaring, in a
sense that the type of the ()'s "result" is always exactly the same as
the type of its "operand". The "operand" of () is always
context-determined. 

*  The syntax of (expr)[a][b][c] for the part select operator (where the
parenthesis may be optional for certain kinds of selected expression)
seem to be the most succinct and flexible syntax suggested, even though
several committee members raised concerns about ability of an uninformed
reader to infer that the "first operand" of the part select given in
such syntax ("(expr)") is self-determined. 


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Received on Mon Mar 12 07:17:53 2007

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