RE: [sv-bc] part selects on arbitrary expressions

From: Feldman, Yulik <yulik.feldman_at_.....>
Date: Mon Mar 12 2007 - 09:32:08 PDT
I'm sorry to say that this is not at all clear. It is all a matter of
definition. One can define it in the way that suits his/her needs the
most. 

For a casual reader, the difference between Verilog's b[0] and b[0:0]
may seem to be only syntactic. Considering that the difference is not
noticeable with packed types, I'm pretty sure that quite a lot of people
do not even imagine that there is also a semantic difference.

--Yulik.

-----Original Message-----
From: Greg Jaxon [mailto:Greg.Jaxon@synopsys.com] 
Sent: Monday, March 12, 2007 6:15 PM
To: Feldman, Yulik
Cc: Bresticker, Shalom; sv-bc@eda.org
Subject: Re: [sv-bc] part selects on arbitrary expressions

Feldman, Yulik wrote:
> Note that "b" is an unpacked array. A one-element unpacked array is
not
> assignment compatible to the type of the element of the array. The
> question is whether the type of "b[0]" and "b[0:0]" is a one-element
> unpacked array or the type of the element itself.
> 
> --Yulik.

Isn't it clear that b[0] and b[0:0] have a different number of
dimensions?
b[0] has one fewer dimensions than b, where b[0:0] has the same number
of
dimensions as b.  If not, please read Trenchard More on the algebra of
array shape.
E.g.: http://portal.acm.org/citation.cfm?id=804440&coll=portal&dl=ACM

Greg Jaxon

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Received on Mon Mar 12 09:32:30 2007

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