[sv-bc] Merged LRM draft review

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Thu Mar 29 2007 - 07:52:31 PDT
  

Hi,

I have not had time to do any serious review of the draft merged LRM,
but here are a few items:

 

1.    In 7 places appear "twos complement" with or without a hyphen
between them. This is an error of the IEEE editor in the 2005 LRM. There
should be an apostrophe after "two" -> "two's". The hyphening should be
consistent.

 

2.    In 5.6.1, "The use of x and z in defining the value of a number is
case insensitive.", z should not be blue or underlined.

 

3.    In the Normative References (Clause 2):
IEEE Std 1364(tm), IEEE Standard for Verilog(r) Hardware Description
Language.

IEEE Std 1364(tm)-2005, IEEE Standard for Verilog Hardware Description
Language.

IEEE Std 1364(tm)-2001, IEEE Standard for Verilog Hardware Description
Language.

IEEE Std 1800(tm), IEEE Standard for SystemVerilog-Unified Hardware
Design, Specification, and Verification Language.

IEEE Std 1800(tm)-2005, IEEE Standard for SystemVerilog-Unified Hardware
Design, Specification, and Verification Language.

The references to 1364 and 1800 without years should not appear.
1364-2001 should appear before 1364-2005, if at all.

 

4.    In Clause 7, the first sentence, "This clause defines structures,
unions and arrays, which can represent aggregate collections of data,"
should be deleted as it duplicates the following paragraph.

 

5.    19.4 (Display tasks) and 19.17 (Enhancements to Verilog system
tasks) should be merged into Clause 20.

 

6.    Consider moving 20.4 ($sdf_annotate) into Clause 33 (SDF),

 

7.    Move Clause 33 (SDF) to after clause 30 (Timing checks).

 

8.    25.1.1 (Built-in package) should move to the end of Clause 25
(Packages). It should be a 2nd-level subclause instead of a 3rd-level
sub-clause. Note that 17.11 now becomes a forward reference to std.
25.1.1 says that std "contains system types (e.g., classes), variables,
tasks, and functions." Actually, it only contains classes and a
function. This sub-clause and Annex G should cross-reference each other.

 

9.    10.7 is Assignment Patterns. I would like to see it combined with
5.10 and 5.11 Structure literals and Array literals, they largely
duplicate each other. I think a better place for this section might be
in clause 7 on structures and arrays.

 

10.          Finally, 27.1.5 and 27.1.6 discuss arrays of instances.
Most of this should go into 22.2, as most of it is applicable to all
kinds of modules (and interfaces). 22.2.3.5 should separate the
discussions of unpacked array ports and arrays of instances and the
discussion of arrays of instances there should be combined with the
general discussion of port connections to arrays of instances.

 

Thanks,

Shalom

 

Shalom Bresticker

Intel Jerusalem LAD DA

+972 2 589-6852

+972 54 721-1033 

 


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Received on Thu Mar 29 07:53:40 2007

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