RE: [sv-bc] MERGE REVIEW draft 2: Chapter 10

>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On 
>Behalf Of Brad Pierce
>Sent: Monday, April 09, 2007 5:16 PM
>To: sv-bc@eda-stds.org
>Subject: [sv-bc] MERGE REVIEW draft 2: Chapter 10
>
>10.1, Table 10-6 --
>
>   Why this mention of "vector net or packed variable"?  Couldn't the
>left-hand side of a continuous assignment be a bit- or part-select of a
>net or variable with an unpacked type?  Or is the claim that the
>following example is illegal?
>
>   typedef int T[3];
>
>   wire T w;
>   var T v;
>
>   assign w[0:1] = '{10,20};
>   assign w[2] = 30;
>
>   assign v[0] = w[2];
>   assign v[1:2] = w[0:1];
>

I, too, had a question about this and Stu challenged me to identify
where
in an LRM this is allowed. The answer starts with 1800-2005, 11.5:

  In Verilog, continuous assignments can only drive nets, and not
variables.

  SystemVerilog removes this restriction and permits continuous
assignments
  to drive nets and variables of any data type.

and continues in 1800-2005, 6.7.

It seems Clause 10 in Draft 2 is removing functionality previously
permitted
in 1800-2005. 

Matt

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