[sv-bc] MERGE REVIEW draft 2: Chapter 7

Intro to 7.1.1 says:

"A structure represents a collection of variable types that can be 
referenced using the structure name."

Technically, I do not think it is true that structures have names in
System Verilog. I think typedefs have names, and structures are usually,
but not always, defined in typedefs. It is also confusing whether this
means the fields can be referenced by name or the whole structure can
be referenced by name.

I would change this to just say

"A structure represents a collection of variable types that can be
referenced
as a whole or the individual variable types that make up the structure
can be
referenced by name."


Intro to 7.1.2:

"A union is a data type that represents a single piece of 
storage which can store one of any variable type."

I would change this to say "single piece of storage which can store
several different variable types."

Section 7.6.10:

The string "Verilog syntax" is struck out, but no replacement is
provided. 
"System Verilog syntax" perhaps.

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