RE: [sv-bc] P1800 draft2 review : Sec 9 Processes

Sure, but that is the example that proves the point. You can't use
'case' directly inside a continuous assignment, so you have to do it in
a roundabout way. It would be simpler to just directly write:

 

always_comb

      case (a)

        ... : return x=b;

        ... : return x=c;

       endcase

 

Shalom

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Brad Pierce
Sent: Tuesday, April 17, 2007 9:04 AM
To: sv-bc@server.eda-stds.org
Subject: Re: [sv-bc] P1800 draft2 review : Sec 9 Processes

 

To use case with assign, you can do

 

    assign x = foo(a,b,c);

    function foo(input a, b, c);

       case (a)

        ... : return b;

        ... : return c;

       endcase

    endfunction

 

-- Brad

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Monday, April 16, 2007 10:50 PM
To: Michael (Mac) McNamara; Gran, Alex; sv-bc@eda-stds.org
Subject: RE: [sv-bc] P1800 draft2 review : Sec 9 Processes

Yes, and it is better at x-propagation, but it is less readable for
complex logic, you can't use case statements or void functions, and it
also creates latches as well as combinational logic.

 

Shalom

 

________________________________

From: Michael (Mac) McNamara [mailto:mcnamara@cadence.com] 
Sent: Monday, April 16, 2007 11:39 PM
To: Bresticker, Shalom; Gran, Alex; sv-bc@eda-stds.org
Subject: RE: [sv-bc] P1800 draft2 review : Sec 9 Processes

 

The declarative assign statement is also quite good at generating
combinatorial logic.

	 

	
________________________________


	From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf
Of Bresticker, Shalom
	Sent: Monday, April 16, 2007 6:16 AM
	To: Gran, Alex; sv-bc@eda-stds.org
	Subject: RE: [sv-bc] P1800 draft2 review : Sec 9 Processes

	Hi,

	 

	9.1.2.2

	    This is a rather nit-picky thing.  Section 9.1.2.2 contains
the sentence "SystemVerilog provides a special always_comb procedure for
modeling combinational logic behavior."

	      What makes always_comb so special, does it think its
better than all the other types of processes? :-)

	     I think this sentence made more sense in 1800-2005 as way
of stating that always_comb was only in SV, not in plain old Verilog,
but in the merged document shouldn't all procedures be created equal?

	 

	[SB] Nope. always_comb is specially tailored for combinational
logic. You can use a plain always, but always_comb is recommended.
'special' means 'special purpose' or 'specialized'.

	 

	 

	 


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