RE: [sv-bc] string == and !=

Good question.

I would say that the following sentence from 4.7 applies:

"Literal strings are implicitly converted to the string type when
assigned to a string type or used in an expression involving
string type operands."

Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
> On Behalf Of Geoffrey.Coram
> Sent: Wednesday, April 18, 2007 8:20 PM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] string == and !=
> 
> I am working on adding string variables to Verilog-AMS,
> following the specification in 1800-2005.  I'm just now
> having a look at Table 4-2, String operators, and I
> have a question about how the comparisons work when
> one string is a string variable and the other is a
> string literal.  For example,
> 
> string mystr = "test";
> 
> if (mystr == "te\0st") $strobe("match");
> 
> If the string literal is first cast to a string type,
> then the "\0" is removed per the rules earlier in
> this chapter, and the equality is true.
> 
> I'm not quite sure what the other alternative is
> (converting the string to a reg of size 8*len(mystr)?).
> Maybe it's non-sensical to have a \0 in a string
> literal.
> 
> -Geoffrey
> 
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