RE: [sv-bc] Proposed changes for 1800-2008 Draft 3

Actually, I had not intended that these be part of the ballot, either
because the comments do not contain a specific proposal or because they
are a lot of work. I do think we should deal with them for the following
draft.

 

Regarding comment 7, in some places 'variable types' and 'variable data
types' refer to variables and in others they refer to data types. Each
place needs to be checked individually.

 

Shalom

 

	SB-O-1. 3.7 and 22.2.1  define "top-level module" slightly
differently.

	SB-O-2. 3.1: "A design element is a SystemVerilog module (see
Clause 22), program (see Clause 22), interface (see Clause 24), package
(see Clause 25), primitive (see Clause 27) or configuration (see Clause
31)." - 31.1 insists that a configuration is a design element, but
almost of all the uses of the term within the LRM, most of which relate
to timescales, are not relevant to configs. 

	SB-O-3. 3.2 lists among the constructs modules can contain:
"procedural blocks", where the reference is to always, initial, etc.
procedures/constructs. Re the discussion about what to call these
constructs, there are a number of places, such as here, where the term
'procedural block' is used, and it will be either awkward or unclear to
just say 'procedure'.

	SB-O-4. String literals are discussed in 5.9 and 11.6.1. Beyond
the basic definition of a string literal, the discussion of what you can
do with them is split up between these two sections roughly evenly, with
some duplication and overlap. The two sections should be unified, or 5.9
should be just a minimal definition of string literals, with all further
discussion in 11.6.1.

	SB-O-5. The discussions of string literals and string types
should be much closer to each other, since they are so closely related.

	SB-O-6. 'Nonprinting and other special characters are preceded
with a backslash.': Does this mean that it is allowed to enter a
nonprinting character directly (preceded by a backslash)? What is
included in 'other special characters'? Is the intent of both of these
only those characters in Table 5-1? What about other special characters?

	SB-O-7. Clause 6 is Data Types. 6.1 starts off nicely with
"SystemVerilog makes a distinction between an object and its data type,
etc." However, later on, the LRM blurs this distinction in terminology
between objects and types. 6.3 is bad in particular, saying "There are
two main groups of data types: the variable data types and the net data
types."  The term 'net data type' only appears 3 times, but 'net type'
appears many times. I think we should be consistent and change most of
the references to them to be 'net objects' or simply 'nets'. Same for
'variable data types' and 'variable types'.

	SB-O-8. 10.7 Assignment Patterns: Combine with 5.10-11 Structure
and Array literals

	SB-O-9. The term 'assignment operator' is not used consistently
in the LRM. It is used sometimes to refer to an entire set of operators,
and sometimes to refer specifically to '='.

	SB-O-10. 22.2.3.5 should separate the discussions of unpacked
array ports and arrays of instances. The discussion of arrays of
instances there should be combined with the general discussion of port
connections to arrays of instances.

	SB-O-11. 35 ("Programming language interface (PLI and VPI)
overview"): On the one hand, VPI is treated as one generation of PLI,
e.g., "Verilog procedural interface routines, called VPI routines, are
the third generation of the PLI," i.e., as being included in the term
'PLI'. On the other hand, it is also treated separately, as in the title
of clause 35, "PLI and VPI". This seems inconsistent and confusing. 

	 


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