RE: [sv-bc] Ballot for proposed changes for 1800-2008 Draft 3

Mark,

> SB1-1-3   yes ___ no _x__ abstain ___
>    I'm confused about what the proposed change is here.

[SB] The proposed change is to correct Clause 1 to describe the contents
of each clause correctly. Clause 1 says that $unit is described in
Clause 25, whereas it is actually described in Clause 3. The mention of
$unit should be moved from the description of Clause 25 to the
description to Clause 3.


> SB1-2-1   yes ___ no _x__ abstain ___
>    I think there may be reasons for somethimes using the year and
> sometimes not.

[SB] The issue is not whether to reference 1364 and 1800 within the LRM
text with or without a year. The issue is whether to list them both ways
in the Normative References clause both ways. It looks ridiculous,
because you have listed the same documents twice.

The ability to list a standard without a date is intended for other
standards, where "for undated references, the latest edition of the
referenced document (including any amendments or corrigenda) applies."
That is nor relevant for previous versions of the same standard,
especially if you have also listed the dated references, which means
that the reference is duplicated.


> SB1-3-3   yes ___ no _x__ abstain ___
>    What is the proposed change. I think a config is a design element.
> I
> don't
>    want it deleted.

[SB] The proposed change is not to delete configs. 3.1 says,

"A design element is a SystemVerilog module (see Clause 22), program
(see Clause 22), interface (see Clause 24), package (see Clause 25),
primitive (see Clause 27) or configuration (see Clause 31). These
constructs are introduced by the keywords module, program, interface,
package, primitive and configuration respectively.

Design units are the primary building blocks used to model and build up
a design and verification environment. These building blocks are the
containers for the declarations and procedural code that are discussed
in subsequent clauses of this document.

This clause describes the purpose of these building blocks."

That last sentence means that Clause 3 is supposed to describe the
purpose of configs, just as it does of every other design element.
The proposed change is therefore to add a subclause which describes the
purpose of configs.


> SB1-6-1   yes ___ no _x__ abstain ___
>     Not clear proposal to vote on.

[SB] The proposal is to change

"6.1 Value set

SystemVerilog makes a distinction between an object and its data type. A
data type is a set of values and a set of operations that can be
performed on those values. Data types can be used to declare data
objects or to define user-defined data types that are constructed from
other data types. A data object is a named entity that has a data value
associated with it, such as a parameter, a variable, or a net.

6.1.1 Logic values"

TO

"6.1 Data types and data objects

SystemVerilog makes a distinction between an object and its data type. A
data type is a set of values and a set of operations that can be
performed on those values. Data types can be used to declare data
objects or to define user-defined data types that are constructed from
other data types. A data object is a named entity that has a data value
associated with it, such as a parameter, a variable, or a net.

6.2 Value set
6.2.1 Logic values"


> SB1-7-1   yes ___ no _x__ abstain ___
>    I prefer my own proposal on this, MH-1

[SB] You are confused. This proposal relates to something different.

The proposal is to change

"7. Aggregate data types

This clause defines structures, unions and arrays, which can represent
aggregate collections of data.

This clause describes:
- Structure definitions and usage
- Union definitions and usage
- Packed arrays, unpacked arrays, dynamic arrays, strings, associative
arrays, and queues
- Array query and manipulation methods"

TO 

"7. Aggregate data types

This clause describes:
- Structure definitions and usage
- Union definitions and usage
- Packed arrays, unpacked arrays, dynamic arrays, strings, associative
arrays, and queues
- Array query and manipulation methods"


> SB1-33-1  yes ___ no _x__ abstain ___
>   I'm confused about what is the exact proposal

[SB] The proposal is to change 

27. Gate-level and switch-level modeling
28. User-defined primitives (UDPs)
29. Specify blocks
30. Timing checks
31. Configuring the contents of a design
32. Protected envelopes
33. Backannotation using the standard delay format (SDF)

TO

27. Gate-level and switch-level modeling
28. User-defined primitives (UDPs)
29. Specify blocks
30. Timing checks
31. Backannotation using the standard delay format (SDF)
32. Configuring the contents of a design
33. Protected envelopes

> BP1-5-3   yes ___ no _x__ abstain ___
>   I'm not sure what 'data object' means.  Can't I assign a string
> literal to a net?

[SB] Data object is defined in 6.1.

Shalom

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.