Date: Thu May 17 2007 - 13:28:06 PDT
Hi, I understand LRM to say that for .name, port and connection types have to be equivalent, but do not have to match. (Names have to be the same). For example, one side could have a[4:3] and the other could have a[2:1]. The LRM seems to be very careful about saying that the *sizes* have to be the same without saying that the exact ranges have to be identical. It also says that the data types have to be equivalent. So the first sentence in 22.3.2.3 seems to be worded awkwardly and confusingly: "SystemVerilog can implicitly instantiate ports using a .name syntax if the instance port name and equivalent type match the connecting declaration port name and type." The 'equivalent type match' in this sentence is not very good. I suggest to reword it to be similar to the corresponding sentence in 22.3.2.4: "SystemVerilog can implicitly instantiate ports using a .* wildcard syntax for all ports where the instance port name matches the connecting port name and their data types are equivalent." So we would get: "SystemVerilog can implicitly instantiate ports using a .name syntax if the instance port name matches the connecting port name and their data types are equivalent." Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
