[sv-bc] Port of a modport can be an another modport ?

Hi,

According to LRM P1800.2005,section 20.4

interface i2;
wire a, b, c, d;
modport master (input a, b, output c, d);
modport slave (output a, b, input c, d);
endinterface

module m (i2.master i);
...
endmodule

Above testcase is valid but can you let me know that whether the 
following testcase is valid or not?

interface i1;
interface i2;
wire a, b, c, d;
modport master (input a, b, output c, d);
modport slave (output a, b, input c, d);
endinterface
i2 tmp1(.*), tmp2(.*);
modport master1 (tmp1.master,tmp1.slave);
modport slave2(tmp2.master,tmp2.slave);
endinterface

module m();
endmodule

Here in above testcase the port of modport is an another modport which 
is declared through hierarchical reference through instance. so is it a 
valid testcase?


Thanks,
Dhiraj



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