[sv-bc] Hier ref through a binded instance.

Hi,
I have seen some discussions are going on for binded instances. I have 
one issue to be clarified.

As per LRM, a binded instance will be inserted to a particular target 
scope or instances. But LRM is not clear whether the binded instance 
will be part of that target scope or instances. Basically I have got 
some cases, where hierarchical reference is done though binded instance 
starting from the target scope. For e.g.

module test();
mid m1();

bind mid prog1 p1(); // bind stmt

initial
test.m1.p1.b1 = 1'b1;
endmodule

module mid( );
endmodule

module prog1;
bit b1;
endmodule

Some of the simulators are passing this type of test case. But I think, 
to support this type of hierarchical reference, any scope variable 
resolution involving instance needs to be stopped until all bind 
construct of the whole design are resolved, which will impact on runtime 
of any tool. Is it a desired behaviour?

-- 
Regards
Surya





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