Mark wrote... > > SVDB 1111 ___Yes _X__No > http://www.eda.org/svdb/bug_view_page.php?bug_id=1111 > I think this will cause a lot of backwards compatibility > issues. Verilog-XL did not check this, and other tools > have been forced to follow Verilog-XL. I think the > standard should reflect what most tools actually > have implemented. > If my failing memory serves me correctly, I recall discussing this when we created Verilog-1995. Everyone, including the company that owned Verilog-XL, agreed that that product had a bug, and that the standard show require that the port size and net/variable size should match. Thus, we specified the sensible rule in the standard, rather than basing the standard on one tool's bug. But Mark is right. Twelve years later, and now that bug is the de facto standard. It would be fully backward compatible to change the standard to say what tools actually do. Specifically, if the port packed range and the net/variable packed range differ, the net/variable packed range is used. Stu ~~~~~~~~~~~~~~~~~~~~~~~~~ Stuart Sutherland Sutherland HDL, Inc. stuart@sutherland-hdl.com 503-692-0898 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Jun 10 22:34:18 2007
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