RE: [sv-bc] Is labeled statement is scope?

In Draft 3, such a statement is found in 16.3.

"The optional statement label (identifier and colon) creates a named
block around the assertion statement (or any other SystemVerilog
statement) and can be displayed using the %m format specification."

Mantis 1348 is about clarifying this and related issues.

Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
> On Behalf Of Surya Pratik Saha
> Sent: Wednesday, June 13, 2007 1:21 PM
> To: sv-bc@eda-stds.org
> Subject: [sv-bc] Is labeled statement is scope?
> 
> Hi,
> Is labeled statement a scope? LRM lists out the valid scopes in 19.13
> (Name spaces), there labeled statement is not included. But some
> simulators implemented labeled statement as a scope. For e.g.
> 
> module top;
> wire clk;
> always @(posedge clk)
> begin : ASSIGN_BLOCK
> my_block: if ((01)&(out1))
>     begin : assert1
>     int a;
>     a=in1;
>     end
>     else
>     begin : assert2
>     int b;
>     b=in2;
>     end
>     end
> endmodule
> module bench;
>     top t();
>     integer x;
>     initial begin
>        x = t.ASSIGN_BLOCK.my_block.assert1.a;
>     end
> endmodule
> 
> Since my_block is a labeled statement, so hierarchical reference on
> that
> is invalid. Though some simulators pass it.
> 
> --
> Regards
> Surya
> 
> 
> 
> 
> 
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