[sv-bc] Query for pattern matching

Hello,

We know that  hierarchical resolution are aspects of elaboration activity.
According to the BNF of pattern matching mentioned in IEEE Std 
1800-2005, IEEE Standard for SystemVerilog:-
cond_pattern ::= expression matches pattern
pattern ::= . variable_identifier

variable_identifier is created  using the type of the expression 
mentioned in cond_pattern.
and LRM does not restrict  for the expression so we can  assume that  
hierarchical reference  can be used as expression.

But if   hierarchical reference is used as expression in cond_pattern 
then variable_identifier is created
after resolving that  hierarchical reference at the time of elaboration 
and all the semantic checks depending upon that variable_identifier will 
be done there after.
That can raise cyclic dependency in some situations.

So my query is - whether hierarchical reference is allowed as 
expression  in cond_pattern  or not?
and for the following testcase ,where  hierarchical reference is used as 
an expression
 in cond_pattern is valid or not?

module mod;
    bit i1[8:0];
    bit k1[8:0];
    bit j1[8:0];
    initial begin
        k1 = mod.i1 matches .n? n : j1;
    end
...

Thanks and regards,

Moumita



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