Date: Sun Jun 24 2007 - 09:47:54 PDT
Hi, I believe there was a discussion not long ago about negative delays. We have a situation where an SDF file is created with negative INTERCONNECT delays. Can that represent a physical reality? (Need circuit engineers for that one...) If so, is there anyway to simulate it? Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
