[sv-bc] Re: [sv-ac] type operator

No, it is the description of 'self-determined expression' that needs to
be fixed or removed.  Bit-widths are not the only aspect of an
operator's type signature that is affected by context in Verilog.

For example, in (e1 * e2) the multiplier is not necessarily signed when
e1 and e2 are signed.  It depends on the context.  For example, in (e1 *
e2) + 1'b0, the multplier is unsigned, regardless of the signednesses of
e1 and e2.

-- Brad

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Doron Bustan
Sent: Tuesday, June 26, 2007 2:17 PM
To: sv-ac@eda.org
Subject: [sv-ac] type operator

Hi,

I took an action item to look at the type operator and see if a similar
definition can be used to determine the type of an expression used as an
actual argument to an un-typed formal argument.

I do not think that helps. In fact I think that something in the
definition of the type operator is broken. In 6.23 it says:

"The type operator applied to an expression shall represent the
self-determined result type of that expression.
The expression shall not be evaluated and shall not contain any
hierarchical references or references to elements of dynamic objects."


but at11.6.1 it says:

"A self-determined expression is one where the bit length of the
expression is solely determined by the expression itself-for example, an
expression representing a delay value."

meaning, self-determined expression define only the number of bits in
the expression, not the type.
Other language at 11.6 implies the same - no specific type may be
inferred.

I think that I will remove the $var from the un-typed formal arguments
in the rewriting algorithm.

Do you think (like me) that the 'type operator' should be fixed?

Doron

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