Re: [sv-bc] Case Statement Enhancement Proposal Idea

Working just from the "context-determined" rules, I could probably
add a chapter or three myself.   So far most of my list comes from
original Verilog, or from spots where the SV LRM was naive about
the seditious properties of the Verilog syntax it adopted.  So, no.
I threw that last thought in as a way to end on an encouraging tone.

Stu's "self-contained" concept for case is a little odd.  I respect
the idea of visually grouping related elements.  There are lots of
ways to achieve that and all of them are only useful to the extent
they get adopted by a broad audience.  If we adopted Stu's proposal,
though, I could extend my chapter on "hiding the gotcha":

case (a)
  a = b;
2'b00, 2'b11:  y1 = ^a;
2'b01:         y2 = ^a;
2'b10:         y3 = ^a;
endcase

I think Stu's proposal requires a compiler temp - one of the usual
suspects we round up whenever a user thinks something else should
have been synthesized.

Greg
Bresticker, Shalom wrote:
> You think so?
> 
> Stu and Don have an entire book on ways this can and does happen, and I
> have an additional list of significant size.
> 
> Shalom
> 
>> The SV language is powerful enough for the designer to hang himself,
>> but thanks to the required warnings, this seldom happens silently
>> anymore.


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