[sv-bc] FW: Proposal for two additional environment parameter functions

Hi,

Please look at this forwarded proposal in the Verilog-AMS committee.

What interests me in this mail is the general idea of this $simprobe
function which is used to construct a hierarchical name from string
constants. I did not examine all the little details.

What 1800 has is the `` operator within macro definitions.

The need for a way to construct an identifier name often comes up, and I
am not sure that `` gives a sufficient solution.

Note that all the arguments are constants, so that all the work can be
done at elaboration time.

Comments?

Thanks,
Shalom

-----Original Message-----
From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of David Miller
Sent: Tuesday, July 10, 2007 5:44 PM
To: Verilog-AMS LRM Committee
Subject: Proposal for two additional environment parameter functions

Hello,
I would like to propose two new environment parameter functions for LRM
2.3

1. $freq
Similar to $abstime, this function will simply return the current
frequency
when doing a small-signal analysis.

[LRM TEXT]
$freq shall return the current frequency used of a small-signal
analysis. The
function shall return zero (0) during DC or transient analysis.


2. $simprobe(instance, param_name [, expression])
Similar to $simparam(), this function will retrieve the value  of a
given
parameter from a given instance. If the instance/parameter does not
exist, it
will stop with an error. If the optional argument <expression> is
specified, it
will return this value in lieu of the error. This function is not
limited to
retrieving values from Spice elements, but also Verilog-AMS instances.

[LRM TEXT]
$simprobe() allows the user to query the value of an element within the
specified instance. The function returns a real scalar value.
The general form of the $simprobe function is:
	$simprobe(instance, param_name [, expression])
	
<instance> is a string constant (either a literal or string parameter).
If the
string is prefixed with a '.' character, then the characters following
the '.'
character make up the full hierarchical name of the instance to query.
If the
first character of the instance string is not a '.', then the string is
the
local name of the instance to query. It is a compilation error to use a
hierarchical instance name where the string is not prefixed with a '.'
character.

<param_name> is the name of the parameter whose value is required. It is
a
string constant (either a literal or string parameter). A parameter can
be any
valid scalar or indexed vector output parameter for the instance in
question.

<expression> is an optional argument. It can be any valid Verilog-AMS
expression. When specified, its value will be returned in case of an
error.

When <instance> is specified in the hierarchical form, <param_name> will
be
retrieved from <instance>. If <instance> or <param_name> does not exist
an
error will be raised. If <expression> has been specified, it's value
will be
returned in lieu of raising the error.

Example:
module grandchild();
   parameter string inst = ".atop.ch";
   analog $strobe("%m: Value of '%s' is %g", inst, $simprobe(inst,"x"));
endmodule
module child();
   real x;
   grandchild gc();
   analog x = 10;
endmodule
module top();
   real x;
   child ch();
   analog x = 5.0;
endmodule

Here (assuming that the top level module top is instantiated as "atop")
module
grandchild() is asking for the value of 'x' from the instance whose
hierarchical name is "atop.gc" The above example will print the
following message:
   atop.ch.gc: Value of '.atop.ch' is 10.0

When <instance> is not specified in the hierarchical form, the hierarchy
will
be search upwards to find a local instance name that matches. Once the
instance
  name has been matched, the value of <param_name> will be retrieved
from that
instance. If <param_name> does not exist in the resolved instance, an
error
will be raised (or <expression> returned if it has been specified).

Example:
module grandchild();
   parameter string inst = "atop";
   analog $strobe("%m: Value of '%s' is %g", inst, $simprobe(inst,"x"));
endmodule
module child();
   real x;
   grandchild gc();
   analog x = 10;
endmodule
module top();
   real x;
   child ch();
   analog x = 5.0;
endmodule

Here module grandchild() is asking for the value of 'x' from the
instance whose
  local name is "atop". The simulator will search up the hierarchy
looking for
an instance called "atop". Once it finds "atop" the value of "x" is
obtained.
If "atop" does not exist in the hierarchy or did not contain a output
parameter
call "x", then an error is raised (or <expression> is returned if
specfied).
The above example will print the following message:
   atop.ch.gc: Value of 'atop' is 5.0


-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
=====================================


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