Surya raises a good point. [Note: I've removed sv-ac from the list, and added sv-ec whose responsibility this is.] > There is an e.g. in the LRM using hierarchical reference > as signal identifier (page no. 218) Clause 15.8; in the new draft 3a it's clause 14.9. > clocking cd1 @(posedge a.clk); > input a.data; > output a.write; > inout state = top.cpu.state; > endclocking > Which is wrong as per BNF. Indeed it is. It seems that this one slipped the net of 890; I'm ashamed I didn't pick it up when EC was working on that. If I don't hear a strong contrary opinion by the end of today, I'll raise a Mantis item to fix this example and the associated text. I believe it is simply wrong. The clockings should be inside the interfaces, or else hierarchical_expression should be used (as with the inout clockvar in the above example). Clockvars cannot have dotted names. I believe the use of @(posedge a.clk) is OK according to the LRM, since it's an example of an "event_expression". -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jul 11 04:51:15 2007
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