Arturo, > I'm sorry if I mislead you. As we discussed in the past, we agreed to > remove the dotted expression forms from the clock-var Don't apologize - I had totally forgotten about 594, which completely deals with the issue. Mea culpa, and thanks to Doug for highlighting it. > I was noting that not all dotted expressions > represent hierarchical expressions. Clearly that's true, but I'm intrigued that you seem to be thinking of the module/program's port of modport type as being something like a struct variable. I had always imagined it to be more like an alias for the interface instance, with special visibility rules imposed by the modport. I need to go away and think harder about that - it has significant impact on some stuff I've been exploring recently. Thanks -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jul 11 11:45:33 2007
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